Analysis of Series-Connected MOSFETs for Gate Delay Optimization
نویسندگان
چکیده
A series-connected MOSFET structure has been analyzed in order to optimize the discharge time of complex CMOS logic gates in a submicrometric technology. The study has been focused to improve discharge time fixing the area of the diffusion region and regarding the operation point of the different transistors in the chain. Results for a 9 series-connected NMOS chain are presented. Effects due to layout restrictions are also taken into account.
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